Google in Talks With Marvell to Build New AI Chips for Inference

The global race for artificial intelligence supremacy has moved from the laboratory to the silicon fabrication plant. In a move that highlights the intensifying competition in the semiconductor sector, Alphabet Inc. is reportedly in deep discussions with Marvell Technology to develop a new generation of custom AI chips. This strategic shift marks a pivotal moment for Google as it seeks to optimize its infrastructure for the massive computational demands of the Gemini era. By partnering with Marvell, a leader in data infrastructure and networking silicon, Google is not just looking for more power; it is looking for a more efficient, scalable, and cost-effective way to deliver AI results to billions of users worldwide. As the industry pivots from the resource-intensive training phase to the continuous demands of inference, this partnership could redefine the landscape of AI hardware and challenge the long-standing dominance of specialized vendors like Nvidia.

Google is reportedly in talks with Marvell Technology to develop two specialized AI chips: a new memory processing unit and an inference-focused Tensor Processing Unit (TPU). This collaboration aims to diversify Google’s custom silicon supply chain, which already includes long-term partners like Broadcom and MediaTek. The goal is to enhance the efficiency of AI inference—the process where trained models generate responses for users—while reducing operational costs and reliance on high-priced third-party GPUs. These new designs are expected to support Google’s massive AI workloads across Search, Gemini, and Google Cloud, with design finalization targeted as early as 2026.

The Strategic Shift to Inference-Specific Silicon

For the past several years, the tech world has been obsessed with the training phase of artificial intelligence. Training a large language model like Gemini or GPT-4 requires thousands of interconnected GPUs running for months, consuming vast amounts of electricity. However, the industry is entering a new phase: the Age of Inference. Once a model is trained, it must be "served" to users. Every time a user asks a question, generates an image, or summarizes a document, the model performs inference. While training is a one-time intensive event, inference happens continuously and scales directly with the number of users. For a company like Google, which serves billions of queries every day, the cost of inference is quickly becoming the dominant expense in their AI budget.

This shift in economics is what drives the reported talks with Marvell. General-purpose graphics processing units (GPUs) are incredibly versatile and powerful, but they are not always the most efficient tools for inference. By designing Application-Specific Integrated Circuits (ASICs) that are "stripped down" to perform only inference tasks, Google can achieve significantly better performance-per-watt and performance-per-dollar. Marvell’s expertise in data infrastructure makes them a natural partner for this endeavor. The goal is to build hardware that provides instant AI answers at a fraction of the current energy cost, ensuring that Google can integrate advanced AI features into Chrome, Gmail, and Android without significantly impacting its bottom line.

Unpacking the Google-Marvell Partnership: MPUs and TPUs

According to reports, the discussions between Google and Marvell focus on two distinct types of silicon. The first is a memory processing unit (MPU). In the world of AI, memory bandwidth is often the primary bottleneck. Even the fastest processor can be slowed down if it cannot move data in and out of memory quickly enough. An MPU designed to work alongside Google’s existing Tensor Processing Units (TPUs) would help manage these data flows more effectively, allowing the main processors to focus on computation rather than data movement. This "memory-centric" architecture is essential for large models that require frequent access to massive parameter sets.

The second chip in development is a brand-new TPU specifically engineered for inference workloads. While Google’s previous TPU generations, such as the recently announced "Ironwood," are capable of both training and inference, a dedicated inference chip allows for deeper optimization. These chips can be optimized for lower precision mathematics, which is often sufficient for inference and consumes much less power than the high-precision calculations required for training. This dual-track approach—improving memory management while deploying specialized inference cores—signals that Google is moving toward a more heterogeneous computing environment within its data centers.

Breaking the Nvidia Monopoly: The Drive for Custom ASICs

Nvidia currently commands a massive share of the AI chip market, with its H100 and B200 GPUs being the gold standard for model development. However, this dominance has created a "bottleneck" for the rest of the industry. GPUs are expensive, and supply remains constrained. Furthermore, because Nvidia’s hardware is designed to be versatile enough for everything from gaming to scientific research, it carries overhead that specialized AI tasks don't necessarily need. For hyperscalers like Google, the high per-unit cost of third-party hardware is a major incentive to bring chip design in-house.

By working with Marvell, Google is executing a "diversification" strategy rather than a simple substitution. Google doesn't intend to stop buying Nvidia hardware entirely; rather, it wants to ensure that it isn't dependent on a single supplier. This gives Google leverage in price negotiations and allows it to tailor its hardware specifically to its software stack. Marvell has a proven track record in this space, having previously helped startups like Groq design their "Language Processing Units" (LPUs). For Marvell, securing a deal with Google would cement its position as a top-tier player in the custom silicon market, moving it closer to the core of global AI infrastructure.

Evolution of the TPU: From Ironwood to the Age of Inference

Google’s journey into custom silicon began more than a decade ago. The first Tensor Processing Unit was deployed internally in 2015, long before the current AI hype cycle. Since then, the TPU has gone through several iterations, each significantly more powerful than the last. The seventh-generation TPU, known as Ironwood, represents the current pinnacle of this development. Ironwood was designed to deliver ten times the peak performance of its predecessor, scaling to superpods of over 9,000 liquid-cooled chips. Google has described Ironwood as the "first TPU for the age of inference," but the talks with Marvell suggest that even more specialization is on the horizon.

The roadmap for Google's silicon now stretches into 2027 and beyond, with plans for 2-nanometer processors to be fabricated by TSMC. The integration of Marvell-designed components into this roadmap suggests a modular approach. Instead of one monolithic chip, Google’s future AI racks might feature a mix of Broadcom-designed training chips, MediaTek-designed mid-range processors, and Marvell-designed inference and memory units. This "best tool for the job" philosophy allows Google to optimize every layer of its infrastructure, from the individual transistor to the massive data center clusters that power Gemini.

Key AI Chip Partner	Primary Strategic Focus
Broadcom	High-performance training TPUs and long-term ASIC development through 2031.
MediaTek	Next-generation TPU-class chips (Zebrafish) targeting lower-cost inference.
Marvell Technology	Memory processing units and dedicated inference-only TPU designs.
Intel	Custom ASIC-based IPUs and Xeon processors for infrastructure offloading.

The Multi-Partner Strategy: Broadcom, MediaTek, and Now Marvell

One of the most interesting aspects of Google’s hardware strategy is its use of multiple design partners. While Broadcom has been the primary partner for the TPU program for years, Google has recently expanded its circle. In early 2026, Google locked in a long-term agreement with Broadcom through 2031, ensuring stability for its core training hardware. However, the reported talks with Marvell and the existing relationship with MediaTek show that Google is building a "multi-supplier architecture." This mirrors the way major automotive companies manage their supply chains, ensuring that no single vendor has enough leverage to dictate terms.

MediaTek’s involvement, specifically on a chip codenamed "Zebrafish," appears focused on cutting costs by 20-30% for the next generation of inference hardware. Marvell’s role would likely complement this by adding advanced memory management and specialized inference capabilities. By pitting these design firms against one another in different segments of the chip program, Google can drive innovation and price competition. This diversified supply chain is becoming the most ambitious in the industry, surpassing the custom silicon efforts of rivals like Amazon and Microsoft.

Cost Dynamics of AI: Training vs. Inference

To understand why Google is so focused on inference, one must look at the shifting cost curves of the AI industry. Training a frontier model is a capital-expenditure-heavy event. It requires a massive upfront investment in hardware and electricity. However, once the training is done, the cost of that specific model doesn't increase unless you decide to train a newer version. Inference, on the other hand, is an operational expense. Its costs are directly tied to user growth. If Gemini goes from 100 million users to 1 billion users, the inference costs scale linearly.

As AI products become integrated into everyday tools like search engines and office suites, the volume of inference queries is exploding. If Google were to rely solely on general-purpose GPUs for these queries, the energy and hardware costs would be unsustainable. Custom inference chips like the ones Marvell is helping to design are essential for "scaled inference." They allow Google to serve hundreds of millions of people simultaneously with minimal latency. For investors, this efficiency is key to proving that Google’s multi-billion dollar AI investments can actually turn a profit.

Global Market Impact: The Custom Silicon Boom

The news of Google's talks with Marvell had an immediate impact on the financial markets, with Marvell’s shares jumping as much as 5.5% following the initial reports. This reflects a broader trend: the custom ASIC market is projected to grow by 45% in 2026 alone, significantly outpacing the growth of the general GPU market. Industry analysts expect the custom chip market to reach $118 billion by 2033. This growth is driven by the fact that as AI use cases become more specific, the hardware must become more specific as well.

This trend isn't limited to Google. Amazon has its Trainium and Inferentia lines, Microsoft has deployed its Maia chips, and Meta has introduced its Meta Training and Inference Accelerator (MTIA). However, Google’s approach is unique due to its depth and the sheer number of partners involved. The shift toward custom silicon is reshaping the semiconductor industry, creating massive opportunities for firms like Marvell, Broadcom, and ARM, while putting pressure on traditional leaders to continue innovating at a breakneck pace.

Technical Deep Dive: How Memory Processing Units Enhance Performance

Why does Google specifically need a "Memory Processing Unit" from Marvell? In traditional computer architectures, the CPU or GPU spends a significant amount of time waiting for data to arrive from memory. In AI workloads, where billions of parameters need to be accessed constantly, this "memory wall" is a major performance barrier. Marvell’s expertise in CXL (Compute Express Link) and high-speed interconnects allows them to design silicon that can pool memory across multiple chips or handle data pre-fetching more intelligently.

By offloading memory management to a dedicated chip, the TPU cores can stay busy nearly 100% of the time. This reduces "idle cycles" and significantly improves the overall throughput of an AI supercomputer. Furthermore, specialized memory units can help manage the high-bandwidth memory (HBM) that is essential for modern AI. As models continue to grow in size, the ability to move data efficiently between storage and compute will be just as important as the raw mathematical speed of the processor itself. This is where Marvell’s heritage in storage and networking becomes a decisive advantage for Google.

Conclusion

Google’s reported discussions with Marvell Technology represent a sophisticated evolution of its hardware strategy. By moving toward a more diversified, multi-partner supply chain, Google is positioning itself to win the long-term war of AI economics. The focus on specialized inference and memory processing units highlights the reality that the "Age of Inference" requires a different architectural approach than the "Age of Training." As custom silicon becomes the backbone of the global AI infrastructure, partnerships like the one between Google and Marvell will be critical in determining which tech giants can scale their AI services most efficiently. For Google, the goal is clear: to build an unshakeable lead in AI efficiency, ensuring that Gemini remains faster, smarter, and more cost-effective than any competitor in the market.

Frequently Asked Questions

1. Why is Google partnering with Marvell specifically?
Google is leveraging Marvell’s expertise in data infrastructure and networking to build specialized chips for inference and memory management. This helps Google diversify its supply chain and reduce reliance on Nvidia and Broadcom.

2. What is the difference between training and inference chips?
Training chips are designed for the high-intensity process of "teaching" an AI model, while inference chips are optimized for "running" the model to generate answers for users more efficiently and at a lower cost.

3. Will this partnership affect Google's relationship with Broadcom?
No, Google recently signed a long-term agreement with Broadcom through 2031. The Marvell partnership is a diversification move intended to cover different segments of the AI hardware market.

4. How does this move impact Nvidia?
While Nvidia remains the leader in AI training, Google’s move to custom inference silicon reduces its need to buy expensive Nvidia GPUs for its daily operations, potentially challenging Nvidia’s long-term dominance in the inference sector.

5. When will these new Marvell-designed chips be available?
Reports suggest that Google and Marvell aim to finalize the designs as early as 2026, with test production and full-scale deployment in data centers likely following in late 2026 or 2027.

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